Hardware Optimization and Implementation of a 16-Channel Neural Tree Classifier for On-Chip Closed-Loop...

Area of Science:

• Biomedical Engineering
• Machine Learning
• Neuromodulation Systems

Background:

• Epileptic seizures require timely detection for effective closed-loop neuromodulation.
• On-chip machine learning (ML) classifiers are crucial for implantable systems.
• Tree-based classifiers offer low memory footprints suitable for hardware implementation.

Purpose of the Study:

• To develop and optimize on-chip ML classifiers for epileptic seizure detection in neuromodulation systems.
• To enhance hardware performance through model compression and efficient feature extraction.
• To evaluate the system's efficacy and resource utilization on a Zynq-7000 SoC.

Main Methods:

• Implemented a Neural Tree (NT) classifier using model compression techniques (weight pruning, weight sharing).
• Designed a feature extraction engine (FEE) utilizing FIR filters and time-division multiplexing.
• Tested the end-to-end system on a Zynq-7000 SoC using pre-recorded patient EEG data (CHB-MIT database).

Main Results:

• Achieved high diagnostic accuracy: 95.7% sensitivity and 94.3% specificity.
• Demonstrated low on-chip memory requirement of 0.59 kB.
• Fabricated design in 65nm CMOS: 174 µW power consumption and 0.16 mm² area.

Conclusions:

• The developed on-chip ML system enables efficient, real-time epileptic seizure detection for closed-loop neuromodulation.
• Model compression and optimized hardware design significantly reduce resource requirements.
• This work represents a significant advancement towards scalable and energy-efficient neuromodulation devices for neurological disorder prediction.