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MicroNAS for memory and latency constrained hardware aware neural architecture search in time series classification
Tobias King1, Yexu Zhou2, Tobias Röddiger2
1Karlsruhe Institute of Technology, TECO, 76131, Karlsruhe, Germany. tobias.king@kit.edu.
Scientific Reports
|March 4, 2025
Summary
This study introduces MicroNAS, a novel hardware-aware approach for designing neural network architectures for time series classification on microcontrollers (MCUs). MicroNAS effectively balances performance and resource constraints, enabling efficient AI on small devices.
Area of Science:
- Artificial Intelligence
- Embedded Systems
- Machine Learning
Background:
- Neural network research on small processors is limited due to the difficulty of designing microcontroller-aware models with memory and runtime constraints.
- Existing methods struggle to optimize machine learning models for resource-constrained microcontrollers (MCUs).
Purpose of the Study:
- To adapt differentiable neural architecture search (DNAS) for time series classification on resource-constrained MCUs.
- To introduce MicroNAS, a novel hardware-aware approach for generating efficient neural network architectures for MCUs.
- To demonstrate the feasibility of Neural Architecture Search (NAS) for MCU-based time series classification.
Main Methods:
- Integration of DNAS, Latency Lookup Tables, Dynamic Convolutions, and a specialized search space for MCU time series classification.
- Development of a hardware-aware system capable of generating neural network architectures within user-defined latency and memory limits.
- Evaluation of MicroNAS across various datasets and microcontrollers under different performance constraints.
Main Results:
- MicroNAS successfully finds trade-offs between latency and classification performance on different microcontrollers.
- On the UCI-HAR dataset, MicroNAS achieved 94.62% accuracy with 25 ms latency and 98.86% with 50 ms on Nucleo-L552ZE-Q.
- MicroNAS demonstrated adaptability to different MCUs, achieving high accuracy on Arduino Portenta with minimal latency.
- Generated architectures performed comparably to state-of-the-art desktop systems on UCI-HAR and SkodaR datasets.
Conclusions:
- MicroNAS enables efficient neural network deployment for time series classification on resource-constrained microcontrollers.
- The hardware-aware approach facilitates the creation of AI models that meet specific latency and memory requirements.
- This work highlights the potential of NAS for advancing AI capabilities in embedded systems.
