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Related Experiment Video

Updated: May 24, 2025

Assembly and Characterization of Biomolecular Memristors Consisting of Ion Channel-doped Lipid Membranes

Assembly and Characterization of Biomolecular Memristors Consisting of Ion Channel-doped Lipid Membranes

Published on: March 9, 2019

A mixed-precision memristor and SRAM compute-in-memory AI processor.

Win-San Khwa¹, Tai-Hao Wen², Hung-Hsi Hsu^1,2

¹Taiwan Semiconductor Manufacturing Company Limited (TSMC), Hsinchu, Taiwan, Republic of China.

|March 5, 2025

Summary

This summary is machine-generated.

This study introduces a novel mixed-precision heterogeneous compute-in-memory (CIM) processor for AI edge devices. It optimizes energy efficiency, accuracy, and speed by intelligently partitioning tasks across different CIM architectures and number formats.

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Area of Science:

Computer Engineering
Artificial Intelligence Hardware
Energy-Efficient Computing

Background:

AI edge devices require high-precision, energy-efficient computation with large storage and fast response times.
Conventional compute-in-memory (CIM) approaches using homogeneous architectures (memristor-CIM, SRAM-CIM) or computation formats (integer, floating-point) face trade-offs in efficiency, storage, latency, and accuracy.
Existing solutions struggle to meet the demanding requirements of modern AI applications on edge devices.

Purpose of the Study:

To develop a mixed-precision heterogeneous CIM AI edge processor that overcomes the limitations of conventional homogeneous designs.
To enable layer-granular/kernel-granular partitioning of network layers among diverse on-chip CIM architectures and computation formats.
To achieve simultaneous optimization across energy efficiency, storage, wakeup latency, and inference accuracy.

Main Methods:

Implementation of a heterogeneous CIM architecture integrating memristor-CIM, SRAM-CIM, and digital units.
Development of a flexible system for layer-granular/kernel-granular partitioning of AI network layers.
Support for mixed-precision computation (integer and floating-point) based on error sensitivity analysis.

Main Results:

Achieved high energy efficiency: 40.91 TFLOPS/W (ResNet-20) and 28.63 TFLOPS/W (MobileNet-v2).
Demonstrated low accuracy degradation: <0.45% for both ResNet-20 and MobileNet-v2.
Attained rapid wakeup-to-response time of 373.52 μs.

Conclusions:

The proposed mixed-precision heterogeneous CIM processor effectively balances energy efficiency, accuracy, and speed for AI edge devices.
Layer-granular/kernel-granular partitioning offers a powerful hardware-level optimization strategy for diverse AI workloads.
This approach provides a cost-effective, foundry-ready solution for next-generation AI edge computing.