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Updated: May 22, 2025

Using Neuron Spiking Activity to Trigger Closed-Loop Stimuli in Neurophysiological Experiments
Published on: November 12, 2019
FPGA implementation of a complete digital spiking silicon neuron for circuit design and network approach
Xinjun Miao1, Xiaojun Ji2, Huan Chen3
1Department of Emergency, Wenzhou Key Laboratory of Cardiopulmonary and Brain Resuscitation and Rehabilitation Application Transformation, Wenzhou Central Hospital, Wenzhou, 325000, China.
Abstract:
When attempting to replicate the same biological spiking neuron model actions of the human brain, the spiking neuron model methodology and hardware realization design for the nervous system of the brain are crucial considerations. This work provides a modified neural modeling of complete Digital Spiking Silicon neuron model (DSSN4D). This model is capable for regenerating the basic attributes of the original model using a simplified power-2 based modeling technique. The suggested spiking neuron model is based on the fundamental power-2 based operations that can be implemented similar to the basic attributes of the main model. Removing the nonlinear parts of the main model (original one) and replacing them with modified ones leads to achieving a low-cost, low-error, and high-frequency digital system rather than the original modeling. A Xilinx Virtex-7 XC7VX690T FPGA board has been thought of and utilized for hardware realization and of the proposed model (this can validate the proposed system). The original and proposed models (in terms of neural activities) exhibit a significant degree of resemblance, according to hardware results. Additionally, greater frequency and low-cost conditions have been attained. Results of implementation indicate that overall savings are higher than for other papers and the original approach. Additionally, the new neural model's frequency, which is roughly 502.184 MHz, is much greater than the original model's frequency, which was 224 MHz. Also, results in hardware level shows that the proposed model takes a maximum 0.01% of the available resources of a Virtex-7 FPGA board.
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