Synaptic and neural behaviours in a standard silicon transistor.

Area of Science:

• Electronics
• Computer Science
• Materials Science

Background:

• Artificial neural networks (ANNs) are increasingly implemented in hardware for energy-efficient computing.
• Current neuromorphic computers use complex circuits with many transistors per neuron and synapse.
• Simplifying these building blocks is crucial for developing more advanced and efficient ANNs.

Purpose of the Study:

• To demonstrate that a single complementary metal-oxide-semiconductor (CMOS) transistor can exhibit neural and synaptic behaviors.
• To develop a simplified, versatile neuro-synaptic random access memory (NS-RAM) cell using minimal transistors.
• To explore the potential for more sophisticated, larger, and energy-efficient ANNs.

Main Methods:

• Biasing a single CMOS transistor in an unconventional manner to induce neural and synaptic functionalities.
• Connecting two CMOS transistors in series to create a versatile 2-transistor NS-RAM cell.
• Utilizing the mature silicon CMOS platform for high-yield, low-variability device fabrication.

Main Results:

• A single CMOS transistor demonstrated tunable neural and synaptic characteristics.
• The developed 2-transistor NS-RAM cell exhibited adjustable neuro-synaptic responses.
• The fabrication process achieved 100% yield and ultra-low device-to-device variability.

Conclusions:

• A simplified 2-transistor cell can effectively emulate neural and synaptic functions, reducing hardware complexity.
• This approach leverages existing CMOS technology for efficient artificial intelligence hardware.
• The NS-RAM cell offers a promising pathway for the next generation of energy-efficient ANNs.