SiC Double-Trench MOSFETs with an Integrated MOS-Channel Diode for Improved Third-Quadrant Performance

Area of Science:

• Semiconductor device physics
• Power electronics
• Materials science

Background:

• Silicon carbide (SiC) MOSFETs are crucial for high-power applications.
• Parasitic bipolar degradation in SiC MOSFETs limits performance.
• Reducing on-resistance and threshold voltage is essential for efficiency.

Purpose of the Study:

• To propose and analyze a novel double-trench SiC MOSFET with an integrated MOS-channel diode (MCD).
• To investigate the impact of MCD integration on device performance, including breakdown voltage and on-resistance.
• To mitigate bipolar degradation and improve the cut-in voltage of the parasitic diode.

Main Methods:

• Technology Computer-Aided Design (TCAD) simulations were employed for device analysis.
• The design incorporates a short channel in the MCD, adjustable via recess depth.
• Analysis focused on the drain-induced barrier-lowering (DIBL) effect and its influence on device characteristics.

Main Results:

• The integrated MCD effectively eliminates bipolar degradation of the parasitic p-i-n diode.
• A significant 69.2% reduction in cut-in voltage (Von) was achieved.
• Specific on-resistance (Ron,sp) and threshold voltage (Vth) were reduced due to alleviated JFET effect.
• Breakdown voltage (BV) remained largely unchanged.
• Gate charge (Qg) increased slightly, leading to a minor rise in switching loss.

Conclusions:

• The novel double-trench SiC MOSFET with MCD offers improved performance by reducing cut-in voltage and on-resistance.
• The design successfully overcomes parasitic bipolar degradation issues.
• While switching losses see a slight increase, the overall benefits suggest potential for advanced power electronic applications.