Improved Hysteresis of High-Performance p-Type WSe₂ Transistors with Native Oxide WO Interfacial Layer

Area of Science:

• Materials Science
• Condensed Matter Physics
• Nanotechnology

Background:

• Atomically thin two-dimensional (2D) semiconductors, such as transition metal dichalcogenides (TMDs), are promising for next-generation electronics.
• Practical applications are limited by challenges in finding suitable gate dielectrics and minimizing interface/oxide traps.
• Tungsten diselenide (WSe2) is a key material in this field, but its integration requires optimized interfaces.

Purpose of the Study:

• To introduce a novel strategy for improving the dielectric interface of WSe2 p-type field-effect transistors (p-FETs).
• To investigate the role of a tungsten oxide (WOx) interlayer in a high-κ hafnium dioxide (HfO2) back gate stack.
• To enhance the performance and reliability of WSe2-based electronic devices.

Main Methods:

• Integration of a native tungsten oxide (WOx) interlayer between WSe2 and a high-κ hafnium dioxide (HfO2) back gate dielectric.
• Fabrication and characterization of WSe2 p-FETs utilizing the novel gate stack.
• Electrical measurements to evaluate device performance, including subthreshold swing (SS) and hysteresis.

Main Results:

• The WOx interlayer effectively acts as a doping layer, adjusting the threshold voltage (VTH).
• Significant improvement in the WSe2-HfO2 interface quality was observed.
• Achieved a near-ideal subthreshold swing (SS) of approximately 68 mV/dec in long-channel p-FETs.
• Marked improvement in device hysteresis within a 6 V gate sweep range.

Conclusions:

• The integration of a WOx interlayer is a viable strategy to enhance the performance of WSe2 p-FETs.
• This approach effectively mitigates interface and oxide traps, leading to near-ideal device characteristics.
• The study provides a pathway for integrating high-κ dielectrics in high-performance 2D electronic devices.