Design of a gate-all-around arch-shaped tunnel-field-effect-transistor-based capacitorless DRAM.

Area of Science:

• Semiconductor device physics
• Materials science
• Solid-state electronics

Background:

• Conventional dynamic random-access memory (DRAM) relies on electric-field-driven charge carrier movement.
• Scaling limitations in traditional DRAM hinder high-density memory applications.
• Tunnel field-effect transistors (TFETs) offer potential for low-power electronics due to their steeper subthreshold swing.

Purpose of the Study:

• To design and analyze a novel capacitorless single-transistor dynamic random-access memory (1T-DRAM) cell.
• To leverage a gate-all-around arch-shaped tunnel field-effect transistor (GAA ARCH-TFET) with an Si/SiGe heterostructure for enhanced memory performance.
• To investigate the potential of this new DRAM architecture as a replacement for conventional DRAM.

Main Methods:

• Device simulation and analysis of a GAA ARCH-TFET structure.
• Incorporation of an Si/SiGe heterostructure to form a quantum well for improved performance.
• Examination of critical device parameters such as source height, channel height, and germanium composition.

Main Results:

• The GAA ARCH-TFET 1T-DRAM achieves a high current ratio of read "1" to read "0" (10^8).
• Demonstrates a retention time exceeding 1 second at 358 K, indicating robust data storage.
• The arch-shaped gate and Si/SiGe heterostructure significantly enhance tunneling and memory characteristics.

Conclusions:

• The proposed capacitorless GAA ARCH-TFET 1T-DRAM exhibits superior performance and low energy consumption.
• The device design is suitable for high-density memory applications due to improved scalability.
• This novel DRAM architecture shows significant promise as a potential replacement for existing DRAM technologies.