Grain size engineering via a Hf_0.5Zr_0.5O₂ seed layer for FeFET memory and synaptic devices

Area of Science:

• Materials Science
• Solid-State Physics
• Electrical Engineering

Background:

• Ferroelectric field-effect transistors (FeFETs) are crucial for non-volatile memory and neuromorphic computing.
• Optimizing ferroelectric properties and device performance remains a key challenge in FeFET development.

Purpose of the Study:

• To investigate the impact of replacement electrode solid phase epitaxy (SPE) and high-temperature atomic layer deposition (ALD) on FeFET characteristics.
• To enhance ferroelectric, memory, and synaptic functionalities of FeFETs through advanced material engineering.

Main Methods:

• Fabrication of top-gate FeFETs utilizing the SPE method for electrode engineering.
• Employing high deposition temperatures during ALD to control film microstructure.
• Characterization of ferroelectric properties, memory window, endurance, and synaptic behavior.

Main Results:

• Reduced grain size and suppressed monoclinic phase formation in the ferroelectric layer.
• Increased remanent polarization (35%) and coercive field (50%).
• Enhanced memory window (0.3 V to 0.9 V), three orders of magnitude improvement in endurance, increased conductance states (100 to 136), and a higher Gmax/Gmin ratio (5.16 to 90).
• Improved weight update linearity and a 20% increase in inference accuracy (65% to 85%) on the MNIST dataset.

Conclusions:

• The combined SPE and high-temperature ALD approach effectively optimizes FeFET performance.
• Engineered FeFETs show significant potential for advanced memory and efficient artificial intelligence hardware acceleration.