Efficient 22 nm GNRFET PTLA using low power trimode technique for high speed processor.

Area of Science:

• Electrical Engineering
• Computer Engineering
• Materials Science

Background:

• Traditional CMOS logic faces limitations in power efficiency for advanced computing.
• Graphene Nano Ribbon Field Effect Transistors (GNRFETs) offer superior carrier mobility and thermal stability.
• Pass transistor logic (PTL) enables transistor count optimization in circuit design.

Purpose of the Study:

• To introduce a new low-power pass transistor logic adder (PTLA) design.
• To leverage 22nm GNRFET technology for enhanced computing performance.
• To optimize power consumption, delay, and area using a trimode technique.

Main Methods:

• Design of 24T PTLA and 21T PTLA configurations using pass transistor logic.
• Integration of a low-power trimode technique for dynamic operational state management.
• Performance evaluation under varying Process Voltage Temperature (PVT) conditions and Monte Carlo analysis.
• Extensive Synopsys HSPICE simulations for optimization and validation.

Main Results:

• The 24T PTLA design achieved a 99.9% reduction in power and a 99.5% reduction in Power-Delay Product (PDP) compared to conventional logic.
• The 21T PTLA design demonstrated a 99.6% enhancement in delay stability and a 99.8% reduction in leakage current.
• The GNRFET-based PTLA exhibits high carrier mobility and temperature resilience.
• Validated adaptability and reliability through PVT and Monte Carlo simulations.

Conclusions:

• The proposed GNRFET-based PTLA designs offer substantial improvements in energy efficiency and performance.
• These designs are highly suitable for power-constrained applications like AI-enabled devices and edge computing.
• The trimode technique further enhances energy efficiency by dynamically managing operational states.