An integrated large-scale photonic accelerator with ultralow latency

Area of Science:

• Integrated photonics
• Silicon photonics
• Photonic computing

Background:

• Integrated photonics, especially silicon photonics, are key for communications, autonomous driving, biosensing, and computing.
• Growing AI demands drive interest in photonic computing, but scaling faces manufacturing and packaging hurdles.

Purpose of the Study:

• To develop a large-scale integrated photonic accelerator to overcome current scaling limitations.
• To demonstrate high-speed and low-latency matrix multiply-accumulate (MAC) operations for AI and complex problem-solving.

Main Methods:

• Designed and fabricated a large-scale integrated photonic accelerator with over 16,000 photonic components.
• Integrated logic, memory, and control functions onto a co-integrated electronics chip.
• Utilized an innovative 2.5D hybrid advanced packaging approach for seamless electronics-photonics integration.

Main Results:

• Achieved high-speed computing up to 1 GHz frequency.
• Demonstrated ultralow latency as low as 3 ns per cycle for matrix MAC operations.
• Successfully integrated photonic and electronic components at a commercial scale.

Conclusions:

• The developed photonic accelerator significantly advances the potential of silicon photonics for AI and high-performance computing.
• The innovative packaging solution enables scalable integration of complex photonic systems.
• This work paves the way for ultralow latency solutions for computationally intensive problems like Ising models.