Low-Jitter Clock Receivers for Fast Timing Applications.

Area of Science:

• Physics
• Electrical Engineering
• Particle Physics

Background:

• Precision timing is critical for advanced scientific applications, including 4D particle tracking, Positron Emission Tomography (PET), and plasma diagnostics.
• The jitter performance of Time-to-Digital Converters (TDCs) is fundamentally limited by the quality of input pulse acquisition and distribution circuits.

Purpose of the Study:

• To evaluate and develop low-jitter clock receiver and distribution circuits for precision timing systems.
• To design and fabricate circuits compatible with radiation environments and cryogenic temperatures.

Main Methods:

• Evaluation of various clock receiver and distribution circuit designs.
• Fabrication of a differential amplifier with resistive loads driving a pseudo-differential clock distribution network.
• Integration into three prototype chips: analog front-end testbed, TDC evaluation, and Low-Gain Avalanche Detector (LGAD) readout.

Main Results:

• The developed clock receiver and distribution circuit exhibits a jitter of less than 2.25 ps-rms.
• The circuit was fabricated using 28-nm CMOS technology, occupying a small area of 2288 µm².
• The design demonstrates radiation tolerance and cryogenic compatibility.

Conclusions:

• The fabricated clock receiver and distribution circuit meets the stringent timing requirements for future precision timing systems.
• This advancement is vital for enhancing the performance of high-energy physics experiments, medical imaging, and fusion research.