An Overview of Substrate Copper Trace Crack Through Experiments, Characterization, and Numerical Simulations

The high input/output demands of memory packages require precise trace width and spacing, posing challenges for contemporary package design. Substrate copper trace cracks are a major reliability issue during temperature cycling tests (TCTs). This study offers a detailed analysis of copper trace crack mechanisms through experimental observations, material characterization, and numerical simulations. Common failure modes of trace cracks are identified from experimental data, pinpointing initiation sites and propagation paths. Young's modulus of copper foil samples is assessed using four testing methods, revealing consistent trends across samples from different substrate suppliers. Sample A with higher E/H values tested via nanoindentation correlated with lower failure rates in the experiment. Stress-strain testing on copper foil was successfully performed at the lower TCT temperature limit of -65 °C, providing vital input for finite element (FE) models. The simulations show strong alignment with trace crack locations under different failure modes. The impact of copper trace width and material properties is illustrated in numerical models by comparing variations in plastic strain responses, which show differences of up to 40% and 30%, respectively. The simulation design of the experiments (DOE) indicates that high-strength solder resist (SR) can significantly enhance temperature cycling performance by reducing SR and copper trace stress and strain by up to 75%. The accumulation of plastic strain in copper traces is predicted to increase up to four times when SR breaks at the crack location, underscoring the importance of SR in copper trace reliability.