An Overview of Substrate Copper Trace Crack Through Experiments, Characterization, and Numerical Simulations

Area of Science:

• Materials Science
• Mechanical Engineering
• Semiconductor Packaging

Background:

• High input/output demands in memory packages necessitate precise trace dimensions, challenging current designs.
• Substrate copper trace cracks are a critical reliability concern during temperature cycling tests (TCTs).

Purpose of the Study:

• To analyze copper trace crack mechanisms in memory packages.
• To identify common failure modes, initiation sites, and propagation paths.
• To evaluate the impact of material properties and design parameters on reliability.

Main Methods:

• Experimental observations and material characterization (including nanoindentation and stress-strain testing).
• Numerical simulations using finite element (FE) models.
• Design of Experiments (DOE) to assess solder resist (SR) performance.

Main Results:

• Higher E/H values in copper foil correlated with lower failure rates.
• FE simulations accurately predicted trace crack locations.
• Variations in trace width and material properties showed significant differences in plastic strain (up to 40% and 30%).
• High-strength SR reduced stress and strain by up to 75%.

Conclusions:

• Solder resist (SR) plays a crucial role in copper trace reliability.
• SR failure significantly increases plastic strain accumulation, highlighting the need for robust SR materials and designs.
• Understanding crack mechanisms and material properties is key to improving memory package reliability.