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Taylor Series Interpolation-Based Direct Digital Frequency Synthesizer with High Memory Compression Ratio.
Kalle I Palomäki1, Jari Nurmi1
1Wireless Research Center, Tampere University, 33720 Tampere, Finland.
Sensors (Basel, Switzerland)
|April 26, 2025
Summary
This study introduces a novel 16-bit quadrature direct digital frequency synthesizer (DDFS) achieving high memory compression (5178:1) and excellent signal purity (-102.9 dBc SFDR) using Taylor series interpolation.
Area of Science:
- Digital Signal Processing
- Integrated Circuit Design
Background:
- Direct digital frequency synthesizers (DDFSs) face challenges in balancing memory compression with output signal purity.
- Efficient phase-to-amplitude conversion is crucial for DDFS performance.
Purpose of the Study:
- To present a 16-bit quadrature DDFS design that enhances memory compression and signal purity.
- To demonstrate the effectiveness of second-order Taylor series polynomial interpolation for phase-to-amplitude conversion in DDFS.
Main Methods:
- Utilized second-order Taylor series polynomial interpolation for phase-to-amplitude conversion.
- Implemented a segmented look-up table (LUT) approach optimized with a Python model.
- Designed and synthesized the DDFS using register-transfer level VHDL and implemented on an AMD Artix 7 FPGA.
Main Results:
- Achieved a memory compression ratio of 5178:1.
- Generated sine and cosine outputs with high spectral purity, reaching a spurious-free dynamic range (SFDR) of -102.9 dBc.
- Required minimal FPGA resources: 107 logic slices and 3 DSP slices.
Conclusions:
- The proposed DDFS design effectively overcomes the trade-off between memory compression and signal purity.
- Second-order Taylor series interpolation offers a resource-efficient method for high-performance DDFS.
- The design demonstrates practical feasibility through FPGA implementation with competitive resource utilization.
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