On Power-Off Temperature Attacks Potential Against Security Sensors.

Area of Science:

• Computer Engineering
• Cybersecurity
• Embedded Systems

Background:

• Embedded systems are vulnerable to fault injection attacks (FIAs) that alter behavior and compromise security.
• The integrity of security detectors is paramount, as attackers may target these mechanisms.
• Existing detectors need evaluation against novel attack vectors like power-off temperature attacks (POTAs).

Purpose of the Study:

• To evaluate the robustness of delay-based digital detectors against power-off temperature attacks (POTAs).
• To investigate the impact of heating cycles on FPGA-based detector characteristics in various power states.

Main Methods:

• Implementation of two attack detectors on Xilinx Artix-7 FPGAs.
• Exposure of FPGAs to heating cycles in power-off, power-on, and inactive (clock-freezing) modes.
• Analysis of detector characteristics and accuracy post-heating cycles.

Main Results:

• Heating cycles in power-off or inactive modes significantly alter FPGA component delays.
• Detector accuracy is reduced following exposure to these heating cycles.
• The integrity and effectiveness of security detectors are compromised by POTAs.

Conclusions:

• Delay-based digital detectors are vulnerable to power-off temperature attacks.
• The integrity of embedded system security mechanisms can be undermined by environmental stresses during power-off states.
• Robustness testing against novel FIAs like POTAs is crucial for secure embedded system design.