Low Power Ternary State Channel Computing-in-Memory Transistor for Federated Learning.

Area of Science:

• Materials Science
• Computer Engineering
• Artificial Intelligence

Background:

• Federated learning (FL) is a privacy-preserving machine learning approach.
• High communication workload and energy consumption are key challenges in FL.
• Ternary weight changes offer a potential solution for reducing FL resource demands.

Purpose of the Study:

• To develop a novel transistor capable of ternary operations for federated learning.
• To demonstrate a computing-in-memory device that reduces communication overhead and energy consumption.
• To investigate the potential of ternary state channel transistors in low-power AI hardware.

Main Methods:

• Fabrication of a ternary state channel computing-in-memory transistor.
• Utilizing a minimum ternary voltage of 5 mV to generate three conductivity states.
• Programming ternary weight changes by detecting a gentle conductivity state.
• Implementing the transistor in a custom federated learning task to measure communication bit reduction.

Main Results:

• The transistor successfully generated three conductivity states at a low voltage (5 mV).
• A gentle conductivity state was observed, enabling single-transistor programming of ternary weights.
• Total communication bits were reduced by 83.3% in the federated learning task.
• The device demonstrated efficient low-power computing capabilities.

Conclusions:

• The ternary state channel transistor is a promising hardware unit for efficient ternary computing.
• This technology can significantly reduce communication workload and energy consumption in federated learning.
• The developed transistor offers a pathway towards more efficient and privacy-preserving AI systems.