Heterogeneous Tapped Delay-Line Time-to-Digital Converter on Artix-7 FPGA

Area of Science:

• Digital electronics
• Embedded systems engineering
• Scientific instrumentation

Background:

• Field-Programmable Gate Arrays (FPGAs) offer cost-effective, high-precision, and rapid development solutions for Time-to-Digital Converters (TDCs).
• TDCs are crucial in scientific disciplines like high-energy physics, autonomous driving, and medical imaging for precise timing measurements.

Purpose of the Study:

• To present a novel 3-tap heterogeneous tapped delay-line (TDL) architecture for FPGA-based TDCs.
• To enhance multi-channel time-of-flight measurement capabilities.
• To achieve superior time resolution and precision compared to existing FPGA TDC designs.

Main Methods:

• Implementation of a 3-tap heterogeneous TDL architecture on a Xilinx Artix-7 FPGA, building upon the open-source jTDC.
• Utilizing a dual-cycle encoding and calibration method combined with jTDC's dynamic caching mechanism.
• Experimental evaluation of the proposed TDC architecture for time-of-flight measurements.

Main Results:

• An optimal 3-tap heterogeneous TDL architecture achieved a resolution of 23.220 ps and a precision of 17.520 ps.
• An optimal 4-tap heterogeneous TDL architecture demonstrated a resolution of 17.530 ps and a precision of 17.213 ps.
• The implemented TDC exhibits single-cycle dead time and multi-channel expansion capabilities.

Conclusions:

• The proposed 3-tap heterogeneous TDL architecture offers a significant improvement in resolution and precision for FPGA-based TDCs.
• This architecture is suitable for demanding multi-channel time-of-flight applications.
• The study provides a valuable comparison with state-of-the-art FPGA TDCs.