Disturbance-Aware On-Chip Training with Mitigation Schemes for Massively Parallel Computing in Analog Deep Learning...

Area of Science:

• Materials Science
• Computer Engineering
• Artificial Intelligence

Background:

• On-chip training in analog in-memory computing (AIMC) promises reduced data latency and personalized learning.
• Analog synaptic devices in crossbar arrays face challenges like non-uniform programming and disturbances during parallel weight updates.
• Disturbances during training are poorly understood, limiting exploration of their impact on performance.

Purpose of the Study:

• To precisely identify and quantify disturbance effects in 6T1C synaptic devices.
• To propose and validate operational schemes for mitigating these disturbances.
• To evaluate the feasibility of disturbance-aware training in large-scale deep learning arrays.

Main Methods:

• Characterization of disturbance mechanisms in 6T1C synaptic devices (oxide semiconductors and capacitors).
• Development and experimental validation of three operational schemes to mitigate disturbance effects.
• Real-time, disturbance-aware training simulations mapping synaptic arrays to convolutional neural networks (CNNs) for the CIFAR-10 dataset.

Main Results:

• Disturbance effects in 6T1C devices were precisely identified and quantified, worsening with device scaling.
• Proposed operational schemes effectively mitigated disturbance effects, validated through device array measurements.
• Disturbance-aware training simulations achieved software-equivalent accuracy on the CIFAR-10 dataset, even with intensified disturbances.

Conclusions:

• Clarifying the disturbance mechanism is crucial for advancing AIMC.
• The proposed mitigation strategies offer a practical solution for reliable on-chip training.
• This approach enables hardware-based deep learning with high accuracy using 6T1C synaptic arrays.