Design methodology for low-power, low-voltage inductor-less Chua's chaotic oscillator.

Area of Science:

• Electronics
• Nonlinear Dynamics
• Integrated Circuit Design

Background:

• Chua's chaotic oscillator is a fundamental circuit for studying chaos.
• Existing designs often suffer from high power consumption and voltage requirements.
• Dynamic Threshold Metal Oxide Semiconductor (DTMOS) technology offers potential for low-power, low-voltage circuit realization.

Purpose of the Study:

• To design and model a low-power, low-voltage Chua's chaotic oscillator.
• To implement the circuit using DTMOS technology for enhanced efficiency.
• To achieve an inductor-free design for simplified fabrication.

Main Methods:

• Utilized a DTMOS-based Dual-X Second-Generation Current Conveyor (DXCCII) as the primary active block.
• Implemented the Chua diode and a synthetic inductor using DXCCII blocks.
• Simulated the proposed circuits using PSPICE with TSMC 180 nm CMOS technology.

Main Results:

• Achieved a low-voltage bias of ±0.2 V and minimal power consumption of 1.58 µW.
• Successfully designed an inductor-free Chua oscillator using only two DXCCIIs.
• Validated the chaotic behavior and V-I characteristics through simulations, confirming theoretical predictions.

Conclusions:

• The proposed DTMOS-based Chua oscillator offers a significant reduction in power and voltage.
• The inductor-free design simplifies fabrication and integration.
• This work demonstrates the effectiveness of DTMOS technology for efficient chaotic circuit design.