Ideal Thickness in 2D van der Waals Multilayers with Vertical Double Side Contacts

Area of Science:

• Materials Science
• Condensed Matter Physics
• Nanotechnology

Background:

• Two-dimensional (2D) van der Waals (vdW) materials exhibit inherent interlayer resistance affecting carrier distribution.
• Electrode placement significantly impacts carrier density across the thickness of 2D vdW materials.

Purpose of the Study:

• To investigate the thickness-dependent carrier density profiles in 2D vdW materials with different contact configurations.
• To explore the role of vertical double-sided contact (VDC) in mitigating interlayer resistance and optimizing carrier transport.
• To determine the optimal thickness for high-performance 2D vdW transistors.

Main Methods:

• Utilized Thomas-Fermi charge screening theory and a resistive network model for theoretical exploration.
• Systematically analyzed carrier density profiles for bottom, top, and VDC configurations.
• Fabricated and characterized back-gated n-type WSe2 transistors with varying thicknesses (4-244 nm) to validate computational findings.

Main Results:

• VDC configuration effectively suppresses interlayer resistance, leading to improved carrier transport.
• A distinct spatial redistribution of carrier density along the thickness was observed under VDC, forming separate bottom and top channels.
• The highest effective mobility was found at approximately 10 nm thickness, with superior electrical properties (mobility, conductivity, on/off ratio) observed between 8-10 nm.

Conclusions:

• VDC offers a promising approach for designing advanced 2D vdW electronic devices by minimizing interlayer resistance.
• Device thickness is a critical parameter for optimizing carrier density and mobility in 2D vdW transistors.
• The findings provide crucial insights for the development of next-generation transistors based on 2D vdW multilayers.