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MCE-HGCN: Heterogeneous Graph Convolution Network for Analog IC Matching Constraints Extraction.

Yong Zhang1,2, Yong Yin1,2, Ning Xu1

  • 1School of Information Engineering, Wuhan University of Technology, Wuhan 430070, China.

Micromachines
|June 27, 2025
PubMed
Summary

We developed a new graph neural network (MCE-HGCN) to efficiently extract matching constraints from analog integrated circuit (IC) netlists. This method improves analog IC layout design by accurately identifying critical matching constraints.

Keywords:
analog ICheterogeneous multi-graphmatching constraintsmixed attentionssmall dataset

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Area of Science:

  • Electrical Engineering
  • Computer Science
  • Artificial Intelligence

Background:

  • Matching constraints are crucial for analog integrated circuit (IC) layout performance.
  • Current methods for extracting these constraints from netlists can be inefficient.
  • Accurate extraction is vital for optimizing circuit performance and reducing design time.

Purpose of the Study:

  • To propose a novel method for accurate and efficient extraction of matching constraints from analog IC netlists.
  • To introduce the heterogeneous matching constraint extraction graph neural network (MCE-HGCN).
  • To enhance the optimization of analog IC layout design.

Main Methods:

  • Mapping netlists into a heterogeneous attribute multi-graph.
  • Developing a mixed-domain attention mechanism to leverage graph topology and node attributes.
  • Employing a support vector machine (SVM) for matching constraint classification.
  • Utilizing a matching filter to remove interference terms.

Main Results:

  • The MCE-HGCN model demonstrates effective convergence, even with small datasets.
  • Achieved a mean F1 score of 0.917 in matching prediction across diverse netlists and circuit types.
  • Showcased significant performance improvements with the inclusion of the attention mechanism and matching filter.

Conclusions:

  • MCE-HGCN accurately and efficiently extracts matching constraints from various analog circuits and processes.
  • The method provides valuable insights for placement guidance in analog IC layout.
  • MCE-HGCN enhances the overall efficiency of analog IC layout design.