Parallel Processing of Sobel Edge Detection on FPGA: Enhancing Real-Time Image Analysis.

Area of Science:

• Computer Vision
• Image Processing
• Hardware Acceleration

Background:

• Object boundary and feature detection are crucial in computer vision.
• Real-time processing is essential for applications like autonomous vehicles and medical imaging, necessitating hardware accelerators.

Purpose of the Study:

• To implement an improved Sobel edge detection algorithm using Verilog for FPGA-based real-time processing of RGB images.
• To reduce algorithmic complexity and architectural utilization through parallel processing and directional approaches.

Main Methods:

• Developed an FPGA-based algorithm using Verilog for the Sobel edge detection.
• Implemented parallel processing of horizontal and vertical Sobel kernels.
• Utilized eight directional approaches to reduce algorithmic complexity.

Main Results:

• The proposed design computes gradient magnitudes for 1028 × 720 RGB images using 3 × 3 pixel windows.
• Parallel processing and algorithmic complex reduction were achieved, leading to reduced architectural utilization.

Conclusions:

• The FPGA-based improved Sobel algorithm enables efficient real-time edge detection for RGB images.
• The design offers a viable hardware acceleration solution for demanding computer vision applications.