A Universal Implementation Approach for Multivalued Logic Gates Based on Negative Transconductance in...

Area of Science:

• Materials Science
• Electrical Engineering
• Computer Science

Background:

• Multiple-valued logic (MVL) offers higher information density but faces hardware limitations.
• Existing MVL hardware, especially for radix > 3, is complex and underexplored.
• Two-dimensional (2D) materials present an opportunity for simplified MVL device structures.

Purpose of the Study:

• To develop a universal approach for constructing higher radix MVL gates.
• To overcome the hardware complexity challenges in practical MVL adoption.
• To demonstrate novel MVL gate families using 2D materials.

Main Methods:

• Exploiting negative transconductance (NTC) effect in series-connected MoS2 and BP transistors.
• Utilizing multiple current valleys in black phosphorus (BP) transistors for logic operations.
• Designing and simulating MVL gates with reduced transistor counts.

Main Results:

• Successfully realized MVL gate families for radix 3, 4, and 5.
• Demonstrated quaternary (r=4) and quinary (r=5) inverters using only 4 and 5 transistors, respectively.
• Achieved higher DC gains and lower power consumption compared to existing designs.

Conclusions:

• The proposed method offers an efficient approach to higher radix MVL gate construction.
• The use of 2D materials simplifies MVL device architecture.
• Established compact models and equivalent circuits facilitate future large-scale MVL system design.