A novel D-latch with low energy consumption in quantum-dot cellular automata technology

Today, the implementation of computer systems and digital circuits is done using CMOS (complementary metal oxide semiconductor) technology, but problems such as high-power consumption and physical limitations of CMOS have led researchers to use the emerging technology such as quantum-dot cellular automata (QCA). In this paper, new structures for D-latch in QCA technology are presented. At first, a D-latch with 25 cells, a cross-sectional area of ​​0.02 µm², delay of 0.5 clock cycle and 22.89 meV energy consumption is presented, and then, using the proposed D-latch, a reset-based D-latch is also proposed, which has more advantages than the previous structures and has only 29 cells, a cross-sectional area of ​​0.02µm² and a delay of 0.5 clock cycles. Then the D-latch with set and reset terminals is proposed, which has better conditions than the previous structures and has only 29 cells, a cross-sectional area of ​​0.02 µm² and a delay of 0.5 clock cycle. The proposed D-latch designs have better energy consumption than previous structures. The simulation of the proposed methods has been done with the help of QCADesigner and QCAPro tools and compared with other designs in terms of area and energy consumption.