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P-N junction

P-N junction

A p-n junction is formed when p-type and n-type semiconductor materials are joined together. At the interface of the p-n junction, holes from the p-side and electrons from the n-side begin to diffuse into the opposite sides due to the concentration gradient. This diffusion of carriers leads to a region around the junction where there are no free charge carriers, known as the depletion region. The charge density within the depletion region for the n-side and p-side can be described by the...

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Related Experiment Video

Updated: May 4, 2026

Fabricating van der Waals Heterostructures with Precise Rotational Alignment

Fabricating van der Waals Heterostructures with Precise Rotational Alignment

Published on: July 5, 2019

High-Performance p-Type 1D Van der Waals Electronics Prepared Through Solution Processing.

Tianchao Guo¹, Xiangming Xu¹, Maolin Chen¹

¹Materials Science and Engineering, Physical Science and Engineering Division, King Abdullah University of Science and Technology (KAUST), Thuwal, 23955-6900, Saudi Arabia.

Advanced Materials (Deerfield Beach, Fla.)

|July 30, 2025

Summary

This summary is machine-generated.

High-performance p-type transistors were fabricated using solution-processed tellurium (Te) nanowires (NWs). Van der Waals (vdW) junctions between Te NWs showed minimal impact on device mobility, enabling large-area electronics.

Keywords:

high mobility large area p‐type semiconductor solution process

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Last Updated: May 4, 2026

Fabricating van der Waals Heterostructures with Precise Rotational Alignment

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Published on: July 5, 2019

Probe Type II Band Alignment in One-Dimensional Van Der Waals Heterostructures Using First-Principles Calculations

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Published on: October 12, 2019

Residue-Free Fabrication of van der Waals Heterostructures of Two-Dimensional Materials

Residue-Free Fabrication of van der Waals Heterostructures of Two-Dimensional Materials

Published on: July 18, 2025

Area of Science:

Materials Science
Nanotechnology
Electronics Engineering

Background:

Solution-based methods offer low-cost, large-scale electronics fabrication but struggle with high-performance p-type transistors.
Van der Waals (vdW) materials enable atomically defined interfaces crucial for efficient charge transport and enhanced device performance.

Purpose of the Study:

To demonstrate high-performance p-type transistors using solution-processed tellurium (Te) nanowires (NWs).
To investigate the impact of vdW junctions on carrier mobility in Te NW-based devices.
To fabricate large-area vdW films of Te NWs for practical electronic applications.

Main Methods:

Fabrication of transistors using individual tellurium (Te) nanowires (NWs).
Characterization of device performance, including mobility and current on/off ratio.
Preparation and testing of large-area 1D Te NWs vdW films.

Main Results:

Individual Te NW transistors achieved high mobilities averaging ≈370 cm²V⁻¹s⁻¹.
Te-Te NW junctions exhibited mobilities comparable to individual NWs, indicating negligible degradation due to vdW contacts.
Large-area Te NW vdW films yielded transistors with average hole mobility of ≈94.9 cm²V⁻¹s⁻¹, subthreshold swing of ≈248.6 mVdec⁻¹, current on/off ratio of ≈10⁴, and low operating voltage of 1 V.

Conclusions:

Solution-processed Te NWs are suitable for high-performance p-type transistors.
vdW contacts in Te NW networks do not significantly impede charge transport, enabling scalable device fabrication.
This work paves the way for advanced solution-processed electronics utilizing vdW materials.