Structurally optimized SiC CMOS FinFET for high-temperature and low-power SoC logic integration.

Area of Science:

• Materials Science
• Electrical Engineering
• Semiconductor Physics

Background:

• Planar silicon carbide (SiC) CMOS technology faces challenges with high subthreshold swing (SS) and threshold voltage (V_th).
• These limitations hinder the development of high-performance SiC-based logic systems for demanding applications.

Purpose of the Study:

• To design a high-temperature-operable binary inverter using optimized SiC-based CMOS FinFETs.
• To overcome the inherent SS and V_th challenges in planar SiC CMOS technology.
• To validate the performance and robustness of SiC CMOS FinFETs at high temperatures.

Main Methods:

• Utilized 3D Technology Computer-Aided Design (TCAD) simulations for structural optimization of SiC-based CMOS FinFETs.
• Incorporated an optimized fin structure into the SiC CMOS architecture.
• Analyzed self-heating characteristics and temperature-dependent behavior (up to 700 K) of V_th and SS.

Main Results:

• Achieved optimized V_th of 1.83 V (n-type) and 2.54 V (p-type) with enhanced SS values of 73.33 mV/decade (n-type) and 77.74 mV/decade (p-type).
• Designed a binary inverter operating at 3.3 V with a noise margin of 0.820 V (300 K) and a gain of 13.3.
• Demonstrated stable inverter operation at 700 K with a noise margin of 0.811 V and a gain of 5.80.

Conclusions:

• Optimized SiC CMOS FinFETs provide a robust solution for high-temperature logic systems.
• The developed FinFET architecture significantly improves performance metrics compared to planar SiC MOSFETs.
• These findings confirm the potential of SiC CMOS FinFETs for next-generation high-temperature applications.