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Updated: Sep 11, 2025

Nanofabrication of Gate-defined GaAs/AlGaAs Lateral Quantum Dots
Published on: November 1, 2013
Design and fabrication of 4 double input NAND gate chip with excellent electrical and physical performances
Lijun Zhang1,2,3,4, Wenqiang Dang5,6, Yu Lu7
1School of Electronic and Information Engineering, Lanzhou Jiaotong University, Lanzhou, 730070, China. zhanglj_81@tsnu.edu.cn.
Abstract:
In order to improve the performances of 4 two-input NAND so that it can be better used in the aerospace application field and in harsh environments, 4 two-input NAND gate chips were designed and successfully fabricated in this paper, based on 1.2 [Formula: see text]m P-well SPDM CMOS technological processes. The N transistors were fabricated in P-well and connected to GND via [Formula: see text]-well. The metal wires of [Formula: see text] use [Formula: see text] substrate to contact [Formula: see text], to increase its anti-locking capability. An ESD protection circuit was designed at the input terminals, prohibiting the terminal of IC chip from being damaged by ESD stress. The performance of the device is superior to that of other similar products in the world.
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