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Scalable Parameter Design for Superconducting Quantum Circuits with Graph Neural Networks.

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We developed a graph neural network (GNN) algorithm for designing superconducting quantum circuits. This approach significantly reduces errors and design time for large-scale quantum chips.

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Area of Science:

  • Quantum Computing
  • Artificial Intelligence
  • Materials Science

Background:

  • Designing large-scale superconducting quantum circuits is complex and challenging for traditional computer-aided design methods.
  • Simulating quantum systems, especially for large qubit counts, requires efficient and scalable computational approaches.

Purpose of the Study:

  • To propose a novel parameter designing algorithm for large-scale superconducting quantum circuits using graph neural networks (GNNs).
  • To demonstrate the algorithm's effectiveness in mitigating quantum crosstalk errors and improving design efficiency and scalability.

Main Methods:

  • Developed a GNN-based parameter designing algorithm employing a 'three-stair scaling' mechanism with two neural network models: an evaluator and a designer.
  • Trained the evaluator on small-scale circuits and the designer on medium-scale circuits for application to large-scale quantum chip design.
  • Considered frequencies of single- and two-qubit gates simultaneously to mitigate quantum crosstalk errors.

Main Results:

  • The GNN-based algorithm achieved a 51% reduction in errors compared to state-of-the-art methods for circuits with approximately 870 qubits.
  • Design time was reduced from 90 minutes to 27 seconds, demonstrating significant improvements in efficiency and scalability.
  • The algorithm effectively mitigated quantum crosstalk errors by optimizing qubit gate frequencies.

Conclusions:

  • The proposed GNNs-based algorithm offers a more efficient, effective, and scalable solution for designing parameters of superconducting quantum chips.
  • This work highlights the advantages of applying GNNs in the design and optimization of superconducting quantum computing hardware.