Technique of mask optimization for achieving the maximal effective litho-CPW

Area of Science:

• Integrated circuit manufacturing
• Computational lithography
• Semiconductor device fabrication

Background:

• Achieving a large process window (PW) is critical for yield in advanced integrated-circuit manufacturing.
• Shrinking critical dimensions necessitate chip-level common process window (CPW) qualification, often requiring lengthy source mask co-optimization (SMO) iterations.
• Current methods face inefficiencies due to repeated SMO re-optimization when CPW is insufficient.

Purpose of the Study:

• To present a novel mask optimization (MO) approach to maximize the effective CPW in each iteration.
• To reduce the number of time-consuming SMO iterations required for chip-level CPW qualification.
• To enhance overall product yield in advanced-node integrated-circuit manufacturing.

Main Methods:

• Acquire an optimized light source through SMO.
• Utilize the optimized light source in subsequent CPW-friendly MO steps.
• Optimize individual mask patterns, followed by corrections for exposure dose, anchor pattern, and cost function for maximal effective CPW.

Main Results:

• The proposed MO technique achieved an 8.79% improvement in CPW compared to traditional MO methods.
• The method automates MO process updates, yielding maximum CPW in each iteration.
• Significantly shortened the turnaround time of the SMO-MO full procedure.

Conclusions:

• The novel MO approach effectively maximizes the common process window (CPW) in integrated-circuit manufacturing.
• This method substantially reduces the computational overhead and time required for source mask co-optimization (SMO).
• The technique offers a pathway to increased product yield and faster design cycles in advanced semiconductor fabrication.