Middle Interlayer Engineered Ferroelectric NAND Flash Overcoming Reliability and Stability Bottlenecks for...

Area of Science:

• Materials Science
• Electrical Engineering
• Semiconductor Physics

Background:

• Ferroelectric transistors are key for next-generation nonvolatile memory due to multilevel storage and low-voltage operation.
• Gate-injection-type ferroelectric transistors offer advantages for 3D NAND flash, but reliability is hindered by complex polarization switching and charge trapping interactions.

Purpose of the Study:

• To address reliability and stability issues in ferroelectric NAND by engineering the gate stack.
• To modulate polarization dynamics and improve the coupling of polarization switching and charge trapping mechanisms.

Main Methods:

• Gate stack engineering with middle interlayers within a HfZrOx matrix.
• Analytical modeling to understand gate stack optimization and device physics.

Main Results:

• Achieved a memory window up to 11 V and operating voltage below 18 V.
• Demonstrated triple-level-cell retention beyond 10 years, disturbance immunity, and 54% reduced threshold voltage variability.
• Reduced program voltage by 20%, enabling aggressive vertical scaling and 25% higher bit density.

Conclusions:

• Engineered gate stacks overcome reliability and stability bottlenecks in ferroelectric NAND.
• Ferroelectric NAND is a scalable and energy-efficient solution for advanced nonvolatile memory.
• The study provides insights for optimizing ferroelectric gate stacks for future memory applications.