Design Strategies for Optimized Bulk-Linearized MOS Pseudo-Resistor

The bulk linearization technique is a design strategy used to extend the linear region of a metal oxide semiconductor field effect transistor (MOSFET) by increasing its saturation voltage through a composite structure and a gate biasing circuit. This allows us to develop compact and flexible pseudo-resistor elements for integrated circuit designs. In this paper we propose a new simple yet effective design approach, focused on the biasing circuit, that optimizes area, offset, and power consumption without altering the design complexity of the original solution. Post-layout simulations verify the presented design strategy, which is then applied for designing a band-pass filter for neural action potential acquisition. Results of harmonic distortion and noise analysis strengthen the validity of the proposed strategy.