Enhancement of On-Current and Reliability in InGaZnO Thin-Film Transistors for Synaptic Circuit Applications through...

Area of Science:

• Materials Science and Engineering
• Semiconductor Device Physics
• Nanotechnology

Background:

• Amorphous InGaZnO thin-film transistors (a-IGZO TFTs) are crucial for displays and emerging electronics.
• Existing a-IGZO TFTs face trade-offs between high on-current and bias stability.
• Gate insulator engineering is key to overcoming performance limitations in a-IGZO TFTs.

Purpose of the Study:

• To develop a nanometer-scale multilayer gate insulator (GI) strategy for simultaneous enhancement of on-current and bias stability in a-IGZO TFTs.
• To investigate the role of individual dielectric materials (Al2O3, TiO2, SiO2) and their layering order in optimizing GI performance.
• To assess the impact of the engineered GI on device-level characteristics and synaptic circuit functionality.

Main Methods:

• Fabrication of multilayer gate insulators using atomic layer deposition (ALD) supercycle modifications with alternating Al2O3, TiO2, and SiO2 layers.
• Optimization of layer ordering within the GI stack to leverage complementary material properties.
• Electrical characterization of fabricated metal-insulator-metal capacitors and a-IGZO TFTs, including on-current, mobility, leakage current, and bias stress stability.
• Evaluation of a 6-transistor 1-capacitor synaptic circuit utilizing the engineered GI for performance and cycling endurance.

Main Results:

• The optimized multilayer GI significantly improved device performance, showing a ~1.76x increase in on-current and a ~1.47x increase in mobility compared to single-layer Al2O3.
• Enhanced bias stability was achieved, with a minimal -5 mV threshold voltage shift under positive bias stress.
• Reduced insulator leakage current and suppressed charge trapping/defect-state density were observed.
• Synaptic circuits demonstrated faster operation and improved weight-update cycling stability.

Conclusions:

• The proposed nanometer-scale multilayer gate insulator engineering strategy effectively addresses the mobility-reliability trade-off in a-IGZO TFTs.
• This optimization enables superior performance for very-large-scale integration (VLSI) circuits and neuromorphic computing applications.
• Strategic material selection and precise layer ordering in the GI stack are critical for achieving enhanced device stability and functionality.