A Scalable Sub-Picosecond TDC Based on Analog Sampling of Dual-Phase Signals from a Free-Running Oscillator.

Area of Science:

• Electrical Engineering
• Integrated Circuit Design
• Signal Processing

Background:

• Accurate time measurements are crucial for various scientific and technological applications.
• Existing time-to-digital converters (TDCs) face limitations in precision, power consumption, and channel density.
• Novel architectures are needed to meet the demands of high-performance detection systems.

Purpose of the Study:

• To present a novel time-to-digital converter (TDC) architecture.
• To demonstrate high precision and linearity in time interval measurements.
• To evaluate the design's suitability for high-channel-density and high-count-rate applications.

Main Methods:

• Developed a TDC based on analog sampling of dual-phase periodic signals from a free-running oscillator.
• Implemented a proof-of-concept Application-Specific Integrated Circuit (ASIC) using 130 nm CMOS technology.
• Characterized the ASIC's performance, including single-shot precision, linearity, power consumption, and count rate.

Main Results:

• Achieved an average single-shot precision of 0.9 ps-rms (best: 0.79 ps-rms) for intervals up to 3 ns.
• Maintained precision below 3.7 ps-rms for intervals up to 25 ns.
• Demonstrated excellent linearity with differential nonlinearity (DNL) of 0.56 LSB and integral nonlinearity (INL) of 1.43 LSB.
• Reported power consumption of approximately 4.1 mW per channel and a maximum count rate of 22 Mcps.

Conclusions:

• The novel TDC design offers exceptional picosecond-level precision and linearity.
• The shareable oscillator and efficient design enable high channel density and low power consumption.
• The architecture is well-suited for advanced detection systems (e.g., silicon pixel sensors, SPADs, LiDARs, time-correlated single-photon counting) and high-count-rate applications.