A Scalable Sub-Picosecond TDC Based on Analog Sampling of Dual-Phase Signals from a Free-Running Oscillator

This work presents a novel time-to-digital converter based on the analog sampling of dual-phase periodic signals generated from a free-running oscillator. A proof-of-concept ASIC, implemented in 130 nm CMOS technology, achieves an average single-shot precision of 0.9 ps-rms for time intervals up to 3 ns, with a best performance of 0.79 ps-rms. It maintains a precision below 3.7 ps-rms for intervals up to 25 ns. The design demonstrates excellent linearity, with a peak-to-peak differential nonlinearity of 0.56 LSB and a peak-to-peak integral nonlinearity of 1.43 LSB. The free-running oscillator is shareable across multiple channels, enabling power consumption of approximately 4.1 mW per channel and efficient area utilization. These features make the design highly suitable for detection systems requiring picosecond-level precision and high channel density, such as silicon pixel sensors, SPADs, LiDARs, and time-correlated single-photon counting systems. Furthermore, the architecture shows strong potential for use in high-count-rate applications, reaching up to 22 Mcps.