Fabrication and dimensional scaling of SiNW-FET array via AFM-LAO lithography and self-limiting oxidation

Silicon nanowires (SiNWs) have emerged as promising candidates for advanced transistor applications due to their exceptional electronic properties, compatibility with standard semiconductor fabrication processes, and scalability toward miniaturized device architectures. In this study, we present a fabrication technique for SiNW-based device using atomic force microscope (AFM) lithography via the local anodic oxidation (LAO) process. To further refine the dimensions of the fabricated SiNWs, a self-limiting oxidation (SLO) process was employed as a post-patterning treatment. This combined approach addresses the limitations of conventional AFM-LAO by enabling dimensional scaling while improving nanowire uniformity and surface quality. The effects of oxidation temperature and the number of SLO cycles were systematically investigated to assess their influence on nanowire morphology and electrical performance. Results demonstrated that the most significant dimensional reduction occurred at 1000 °C after three SLO cycles. Electrical characterization through I-V measurements revealed a reduction in drain-source current (I_ds), which corresponds to an increase in channel resistance due to decreased nanowire cross-sectional area. This behaviour is consistent with expected nanoscale device physics, where reduced dimensions enhance surface-to-volume ratio and electrostatic control. These findings underscore the effectiveness of the proposed fabrication strategy for improving the structural and electrical performance of SiNW-based field-effect transistor.