Test pattern optimization scheme based on Hybrid Ant Colony Optimization

Area of Science:

• Electrical Engineering
• Computer Science
• VLSI Design

Background:

• Device miniaturization increases digital circuit testing complexity.
• High switching activity during testing leads to elevated power consumption.
• Minimizing transitions between test patterns is key for reducing test power.

Purpose of the Study:

• To propose a Hybrid Ant Colony Optimization (HACO) technique for reducing power consumption in sequential circuit testing.
• To optimize test patterns by reducing their count and reordering them to lower switching activity.

Main Methods:

• Integrating Ant Colony Optimization (ACO) with Kullback-Leibler (KL) divergence for test pattern reduction.
• Employing Prim's algorithm for reordering test patterns to minimize transitions.
• Utilizing ISCAS'89 benchmark circuits for experimental evaluation.

Main Results:

• Achieved a 71.60% reduction in transition count compared to conventional ACO.
• Attained an average power reduction of 57.48% versus Linear Feedback Shift Register (LFSR) generated patterns.
• Demonstrated significant effectiveness in low-power VLSI testing.

Conclusions:

• The proposed HACO technique effectively reduces power consumption during sequential circuit testing.
• This method offers a promising approach for optimizing test patterns in modern digital circuits.
• HACO provides substantial improvements in transition count and power reduction for VLSI testing.