A Phase-Adjustable Noise-Shaping SAR ADC for Mitigating Parasitic Capacitance Effects from PIP Capacitors

Area of Science:

• Electrical Engineering
• Microelectronics
• Analog Circuit Design

Background:

• Parasitic capacitance in poly-insulator-poly capacitors within CMOS processes limits high-resolution SAR ADC performance in imaging.
• This bottleneck hinders the development of advanced imaging systems requiring precise analog-to-digital conversion.

Purpose of the Study:

• To propose a Phase-Adjustable SAR ADC with a reconfigurable architecture to mitigate parasitic capacitance effects.
• To enable a trade-off between high-speed operation and high-resolution conversion in SAR ADCs.

Main Methods:

• A novel phase-adjustable logic unit was designed to switch between conventional SAR and noise-shaping (NS) SAR modes.
• The improved SAR logic unit enabled adjustable phase insertion and an 86% reduction in core logic area.
• A prototype was fabricated using a 0.35-µm CMOS process for performance evaluation.

Main Results:

• In conventional mode, the ADC achieved 7.69 effective bits at 2 MS/s.
• Activating noise-shaping mode enhanced resolution to 11.06 bits (68.3 dB SNDR) at 125 kS/s.
• The design demonstrated effective suppression of in-band quantization noise.

Conclusions:

• The proposed Phase-Adjustable SAR ADC architecture successfully addresses parasitic capacitance limitations in CMOS processes.
• This reconfigurable design offers a practical solution for achieving high-performance ADCs by balancing speed and accuracy.
• The study provides a viable method for realizing high-resolution imaging systems despite non-ideal passive components.