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Design Example: Capacitance Multiplier Circuit

Design Example: Capacitance Multiplier Circuit

In integrated circuit technology, a capacitance multiplier is often utilized to produce a larger capacitance value when a small physical capacitance falls short. This is achieved by a circuit that multiplies capacitance values by a factor of up to 1000, such that a 10-pF capacitor can replicate the performance of a 100-nF capacitor.
The circuit illustrated in Figure 1 below incorporates two op-amps, with the first operating as a voltage follower and the second acting as an inverting amplifier.

Cascaded Op Amps

Cascaded Op Amps

Operational amplifiers (op-amps) are versatile electronic components that can be interconnected in a cascade - one after another in a linear sequence. This cascading is possible due to their infinite input resistance and zero output resistance, allowing them to maintain their input-output relationships even when connected in series.
In a cascaded system, each op-amp is referred to as a stage. The output of one stage drives the input of the subsequent stage. As the input signal passes through...

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Related Experiment Video

Updated: Jan 15, 2026

Fabrication of Flexible Image Sensor Based on Lateral NIPIN Phototransistors

Fabrication of Flexible Image Sensor Based on Lateral NIPIN Phototransistors

Published on: June 23, 2018

An Area-Efficient Readout Circuit for a High-SNR Triple-Gain LOFIC CMOS Image Sensor.

Ai Otani¹, Hiroaki Ogawa¹, Ken Miyauchi^1,2

¹Research Organization of Science and Engineering, Ritsumeikan University, 1-1-1 Noji-Higashi, Kusatsu 525-8577, Japan.

Sensors (Basel, Switzerland)

|October 16, 2025

Summary

This study introduces an area-efficient readout circuit for triple-gain lateral overflow integration capacitor (LOFIC) CMOS image sensors (CIS). The new design improves signal-to-noise ratio (SNR) performance in high-dynamic-range (HDR) imaging.

Keywords:

CMOS image sensor HDR LOFIC high SNR readout circuit

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Last Updated: Jan 15, 2026

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Area of Science:

Electrical Engineering
Computer Vision
Semiconductor Devices

Background:

High-dynamic-range (HDR) imaging is crucial for advanced visual applications.
Lateral overflow integration capacitor (LOFIC) CMOS image sensors (CIS) offer HDR capabilities by combining high-conversion-gain (HCG) and low-conversion-gain (LCG) signals.
A drop in signal-to-noise ratio (SNR) occurs at the HCG-to-LCG signal switching point due to pixel noise in LCG signals.

Purpose of the Study:

To propose an area-efficient readout circuit for triple-gain LOFIC CIS.
To address the SNR drop issue in dual-gain LOFIC CIS.
To enhance HDR imaging performance in CMOS image sensors.

Main Methods:

Developed a novel readout circuit for triple-gain LOFIC CIS.
Employed amplifier and capacitor sharing techniques for HCG, middle-conversion-gain (MCG), and LCG signal processing.
Fabricated a test chip using a 0.18μm CMOS process.

Main Results:

Achieved an area overhead of only 7.6% for the proposed readout circuit.
Improved the SNR drop by 8.05 dB compared to dual-gain LOFIC CIS readout circuits.
Demonstrated the feasibility of the area-efficient design through chip fabrication.

Conclusions:

The proposed area-efficient readout circuit effectively processes triple-gain LOFIC CIS signals.
The design significantly mitigates the SNR drop, enhancing HDR imaging quality.
This advancement offers a practical solution for next-generation CMOS image sensors.