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Short Channel 2D FET with Sloped Architecture
Junsung Byeon1, Jinhyeok Pyo2, Jungmoon Lim1
1Department of Physics, Sungkyunkwan University (SKKU), Suwon, Gyeonggi-do 16419, Republic of Korea.
ACS Applied Materials & Interfaces
|October 17, 2025
Summary
Researchers developed a novel sloped architecture for short-channel field-effect transistors (FETs) using 2D transition metal dichalcogenides (TMDCs). This lithography-free method enables nanometer-scale transistors with enhanced performance and simplified fabrication.
Area of Science:
- Semiconductor industry
- Materials science
- Nanotechnology
Background:
- Miniaturization of electronic devices is key for performance and cost reduction in semiconductors.
- High-resolution lithography for extreme scaling is complex and time-consuming.
- Two-dimensional transition metal dichalcogenides (2D TMDCs) offer potential for short-channel transistors due to their atomic thinness.
Purpose of the Study:
- To realize nanometer-scale channel lengths in 2D TMDC-based field-effect transistors (FETs) without lithography.
- To mitigate short-channel effects (SCE) for improved transistor performance.
- To develop an innovative and simplified fabrication pathway for nanoscale FETs.
Main Methods:
- Constructed a sloped architecture for nanometer-scale channel length in 2D TMDC FETs.
- Utilized hexagonal boron nitride (h-BN) tunneling layers.
- Fabrication was achieved without traditional lithography techniques.
Main Results:
- Achieved nanometer-scale channel length using a sloped architecture.
- Mitigated short-channel effect (SCE) through h-BN tunneling layers.
- Demonstrated a high on-off ratio (>10^5) and low subthreshold swing (SS) of 160 mV/dec.
- Reported an on-current of 3.70 μA.
Conclusions:
- The sloped architecture FET (SSFET) provides an innovative pathway for realizing nanometer-scale FETs.
- This lithography-free approach simplifies fabrication processes.
- The developed SSFET exhibits excellent electrical characteristics, suitable for advanced electronic devices.
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