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Updated: Jan 14, 2026

Ohmic Contact Fabrication Using a Focused-ion Beam Technique and Electrical Characterization for Layer Semiconductor Nanostructures
Published on: December 5, 2015
Ohmic contact engineering for two-dimensional material-based field-effect transistors: recent advances and
Zichao Ma1, Jiwei Chen1, Zhixin Chen1
1School of Microelectronics, South China University of Technology, Guangzhou, People's Republic of China.
Abstract:
The low-resistance ohmic contacts is recognized as one of the most critical challenges in the advancement of high-performance two-dimensional (2D) material-based field-effect transistors (FETs). The metal-2D contacts are confronted by two major obstacles: persistent Fermi-level pinning at contact interfaces and the limited approaches available for modulating the energy level alignment between the metal and the 2D materials. In this review, a comprehensive overview is presented of recent breakthroughs in the understanding and engineering of ohmic contacts for 2D FETs. The underlying physics of contact resistance is systematically examined, with particular emphasis on updated interpretations of Fermi-level pinning effect and innovative methodologies for Schottky barrier modulation. Subsequently, various engineering approaches are critically evaluated, including interface modification techniques, semimetallic contact architectures, and advanced doping strategies that have been extensively engaged to address these challenges. While significant progress has been made in reducing contact resistance for n-channel 2D FETs, achieving reliable p-type Ohmic contacts remains substantially more challenging. Recent investigations of unique physical mechanisms at metal-2D interface, combined with contact structure optimization, have enabled simultaneous improvements in both contact resistance and transistor switching characteristics. These developments highlight the need for coupled theoretical and experimental optimization that focus on interface quality control, scalable integration, and testing protocols to fully realize the potential of 2D semiconductors in next-generation transistor technology.
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