An overhead-reduced, efficient, fully analog neural-network computing hardware.

Area of Science:

• Neuromorphic engineering
• Computer architecture
• Artificial intelligence hardware

Background:

• The von Neumann bottleneck limits energy efficiency in conventional computing.
• Existing neural network hardware lags behind the brain's efficiency due to lack of data compression and analog operation.
• Bridging the gap requires novel hardware designs inspired by biological systems.

Purpose of the Study:

• To develop fully analog neural-network computing hardware (FANCH) with integrated data compression.
• To demonstrate the feasibility of FANCH at both chip and system levels.
• To improve energy efficiency and reduce resource overhead in neural network computation.

Main Methods:

• Fabrication of FANCH using fully analog circuits for complete neural network computation.
• Implementation of input data compression within the analog hardware.
• Evaluation of FANCH performance on handwritten digit recognition tasks.

Main Results:

• FANCH achieved high accuracy in handwritten digit recognition, with only a 0.36% drop from software baselines.
• Demonstrated significant energy efficiency advantages over state-of-the-art AI accelerators.
• Successfully implemented at both chip and system levels.

Conclusions:

• FANCH offers an efficient, fully analog hardware solution for neural network computing.
• The proposed design overcomes limitations of traditional architectures for edge computing.
• This approach paves the way for brain-inspired, low-power AI hardware.