EAAUnet-ILT: A Lightweight and Iterative Mask Optimization Resolution with SRAF Constraint Scheme.

Area of Science:

• Semiconductor Manufacturing
• Computational Lithography
• Deep Learning Applications

Background:

• Integrated circuit feature sizes continue to shrink, making advanced resolution enhancement techniques (RET) like inverse lithography technology (ILT) critical.
• Current ILT methods, including machine learning and gradient descent, struggle to balance mask optimization quality with computational time.
• A common trade-off exists between imaging fidelity and manufacturability in ILT, where prioritizing fidelity increases mask complexity, while manufacturability constraints reduce fidelity.

Purpose of the Study:

• To develop an efficient and effective ILT framework that overcomes the limitations of existing methods.
• To accelerate the runtime and reduce computational overhead associated with mask optimization.
• To improve mask quality metrics and reduce manufacturing complexity for advanced semiconductor fabrication.

Main Methods:

• An iterative deep learning-based ILT framework utilizing a lightweight model, the ghost and adaptive attention U-net (EAAUnet).
• Progressive mask quality improvement through multiple iterations using a pre-trained network model.
• Implementation of a mask constraint scheme to manage complex sub-resolution assist feature (SRAF) patterns.

Main Results:

• The proposed EAAUnet framework significantly accelerates runtime and reduces computational overhead.
• Achieved up to a 39% improvement in mask quality metrics compared to state-of-the-art ILT solutions.
• The mask constraint scheme effectively reduced the complexity of SRAF patterns, enhancing manufacturability.

Conclusions:

• The iterative deep learning framework with EAAUnet offers a superior solution for ILT, balancing optimization quality, computational efficiency, and manufacturability.
• This approach addresses critical challenges in advanced semiconductor manufacturing by improving mask pattern fidelity and reducing complexity.
• The developed method represents a significant advancement in ILT for next-generation integrated circuit fabrication.