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Doping-Free Monolithic 2D CMOS Logic by Fermi-Level Engineering via Tellurium Buffer-Layer.

Hao Liu1,2, Lingan Kong1, Xiaolong Meng1,2

  • 1Songshan Lake Materials Laboratory, Dongguan, 523808, China.

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This study introduces a novel doping-free CMOS fabrication method using a tellurium buffer layer to achieve polarity control in 2D semiconductors. This breakthrough enables efficient complementary logic circuits for next-generation electronics.

Keywords:
2D semiconductorsdoping‐free CMOS invertersinterface engineeringpolarity controltellurium buffer‐layer

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Area of Science:

  • Materials Science
  • Semiconductor Physics
  • Nanoelectronics

Background:

  • Two-dimensional (2D) semiconductors are promising for post-Moore complementary-metal-oxide semiconductor (CMOS) technology.
  • Achieving efficient polarity modulation in doping-free CMOS circuits with 2D semiconductors is challenging due to interface defects and Fermi-level pinning (FLP).

Purpose of the Study:

  • To develop a doping-free CMOS fabrication strategy for 2D semiconductors enabling efficient metal-dependent polarity modulation.
  • To overcome FLP and interface issues in 2D semiconductor-based CMOS devices.

Main Methods:

  • A tellurium (Te) buffer-layer-assisted thermal deposition technique was employed.
  • A sacrificial Te buffer layer was introduced before metal deposition and removed via annealing to create a quasi-van der Waals (vdW) interface.
  • High-work-function gold (Au) metal was used to modulate the 2D semiconductor polarity.

Main Results:

  • The developed method achieved work-function-dependent polarity control on the same 2D semiconductor, overcoming FLP-dominated n-type behavior.
  • A fabricated CMOS inverter demonstrated a voltage gain of 165 at a 5V bias and a 95% total noise margin.
  • The technique is compatible with scalable, industry-standard CMOS manufacturing and back-end-of-line (BEOL) processes.

Conclusions:

  • This study presents a foundational framework for 3D monolithic integration through Fermi-level engineering in 2D semiconductors.
  • The developed approach paves the way for next-generation vertically integrated nanoelectronics.
  • The Te buffer-layer strategy enables efficient polarity control and enhances charge transport in 2D CMOS devices.