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FPGA-based hardware implementation of integrated FEC equalization in bandwidth-efficient IM/DD optical
Optics Express
|November 11, 2025
Summary
This study introduces a novel integrated forward error correction (FEC) equalization scheme using polar decoded decision least mean square (PD-LMS) for optical PAM4 systems. The PD-LMS method enhances receiver sensitivity and significantly reduces hardware complexity.
Area of Science:
- Optical communications
- Signal processing
- Error correction coding
Background:
- Intensity modulation direct detection (IM/DD) optical systems face challenges with inter-symbol interference (ISI) due to limited bandwidth.
- Pulse Amplitude Modulation with 4 levels (PAM4) is crucial for high-speed optical interconnects but is sensitive to signal degradation.
- Existing equalization techniques may not fully address both ISI mitigation and error correction efficiency.
Purpose of the Study:
- To propose and experimentally validate an integrated forward error correction (FEC) equalization scheme for optical PAM4 systems.
- To leverage polar codes within a decision-assisted least mean square (LMS) algorithm for enhanced performance.
- To reduce hardware complexity in practical implementations.
Main Methods:
- Development of a polar decoded decision least mean square (PD-LMS) algorithm.
- Integration of FEC capabilities with equalization for iterative weight optimization.
- Experimental demonstration in a 160 Gb/s optical PAM4 system with a 5 GHz bandwidth.
- Implementation on a field-programmable gate array (FPGA) platform with a reliability-driven pruning scheme.
Main Results:
- The PD-LMS scheme effectively mitigates inter-symbol interference (ISI).
- A 1 dB improvement in receiver power sensitivity was achieved.
- A significant 67% reduction in FPGA hardware computational complexity was realized.
- Simultaneous equalization and FEC reliability enhancement were demonstrated.
Conclusions:
- The proposed integrated FEC equalization strategy offers a robust solution for high-speed optical interconnects.
- PD-LMS provides an effective method for balancing equalization performance and hardware efficiency.
- The reliability-driven pruning scheme is key to simplifying FPGA implementation without compromising performance.
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