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An energy efficient processor array and memory controller for accurate processing of convolutional neural

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Summary

A new controller efficiently manages unstructured sparsity in Convolutional Neural Networks (CNNs) Fully Connected (FC) layers, boosting energy efficiency during inference. This hardware accelerator design improves data movement and achieves significant performance gains.

Keywords:
CompressionConvolutional neural networkDataflowDeep learningEnergy-efficient acceleratorImage classificationSparsity

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Area of Science:

  • Computer Engineering
  • Artificial Intelligence
  • Hardware Acceleration

Background:

  • Exploiting unstructured sparsity in Convolutional Neural Networks (CNNs) hardware accelerators can enhance energy efficiency for inference.
  • Managing unstructured sparsity, especially in Fully Connected (FC) layers, typically requires complex controllers for indexing and load-balancing.

Purpose of the Study:

  • To design and evaluate a novel controller for managing unstructured sparsity in FC layers of CNNs.
  • To improve energy efficiency and data-movement rates in hardware accelerators for CNN inference with minimal hardware overhead.

Main Methods:

  • Introduced approximately 20% sparsity into a pre-trained Visual Geometry-Group-16 (VGG-16) model using an induced sparsity mechanism.
  • Developed a Combined IFM & Weights - Zero Valued Compression (CIW-ZVC) controller to manage data movement between off-chip and on-chip memory.
  • Utilized a processor array with 256 Convolution Operators (COs) and parallel computations with zero-gating on weights, employing a tile-based computation strategy with stationary Input Feature Maps (IFMs).

Main Results:

  • Achieved 95% classification accuracy and a 0.96 harmonic mean of precision and recall on the ImageNet dataset.
  • The CIW-ZVC controller improved data-movement rates with minimal hardware overhead.
  • The 14nm implementation demonstrated a peak performance of 256 x 10^9 Operations/Second (OPS) and energy efficiency of 15 x 10^12 OPS/Watt per FC (VGG-16) layer.
  • Reported up to 6.08 times improvement in energy efficiency and 7.6 times in area efficiency compared to existing processors.

Conclusions:

  • The designed controller effectively manages unstructured sparsity in FC layers, significantly enhancing energy and area efficiency.
  • The proposed hardware acceleration approach offers substantial performance improvements for CNN-based inference.
  • This method provides a viable solution for optimizing deep learning inference on hardware accelerators by addressing sparsity challenges.