A CMOS Voltage Reference with PTAT Current Using DIBL Compensation for Low Line Sensitivity.

Area of Science:

• Integrated Circuit Design
• Analog Electronics
• Semiconductor Devices

Background:

• Stable voltage and current references are critical for analog and mixed-signal circuits.
• Conventional designs often struggle with supply voltage variations, impacting performance.
• Low power consumption is a key requirement for modern portable and embedded systems.

Purpose of the Study:

• To present a novel low-power CMOS voltage reference with enhanced line sensitivity (LS).
• To incorporate a Drain-Induced Barrier Lowering (DIBL)-based compensation path for improved LS.
• To simultaneously provide a stable reference voltage and bias current.

Main Methods:

• Design and verification of a circuit in 180 nm standard CMOS technology.
• Integration of a DIBL-based LS compensation path into a PTAT (Proportional To Absolute Temperature) current generation circuit.
• Simulation of performance metrics including line sensitivity, temperature coefficient, and power supply rejection ratio.

Main Results:

• Achieved LS of 0.01%/V for voltage reference and 0.07%/V for bias current reference.
• Operates over a supply voltage range of 1.4 V to 2 V.
• Generated a 538 mV reference voltage and 38 nA PTAT current with only 68 nW power consumption.
• Simulated temperature coefficient of 58 ppm/°C (-40 °C to 130 °C) and PSRR of -59 dB at 100 Hz.

Conclusions:

• The proposed circuit effectively compensates for line sensitivity in both voltage and current references.
• The design achieves excellent low-power performance and stability over a wide temperature range.
• This work offers a robust solution for low-power, high-performance voltage and current reference needs in integrated circuits.