A Cryptographic Transistor with Stochastic Carrier Trapping and Detrapping for a True Random Number Generator.

Area of Science:

• Solid State Physics
• Microelectronics
• Cryptography

Background:

• True random number generators (tRNGs) are crucial for secure communication.
• Existing tRNGs often require complex fabrication or specialized materials.
• CMOS technology offers a scalable platform for integrated security solutions.

Purpose of the Study:

• To demonstrate a CMOS-compatible cryptographic transistor (cryptosistor) as a tRNG.
• To exploit carrier dynamics at engineered interfaces for randomness generation.
• To integrate a high-performance tRNG into standard semiconductor fabrication.

Main Methods:

• Utilized a cryptosistor based on CMOS technology with a destabilized gate oxide-silicon interface.
• Employed a thin tetraethyl orthosilicate (TEOS) layer for its unstable interface properties to enhance randomness.
• Digitized the irregular voltage output using a low-power analog-to-digital converter (ADC).

Main Results:

• The cryptosistor successfully generated true random numbers, passing the NIST SP 800-22 randomness test.
• Three distinct entropy sources (impact ionization, carrier jitter, trapping/detrapping) contribute to the generated randomness.
• The device integrates seamlessly into standard CMOS fabrication without additional steps.

Conclusions:

• The cryptosistor offers a practical and scalable solution for on-chip true random number generation.
• This approach leverages TEOS as a functional material for enhanced security in hyper-connected environments.
• The demonstrated tRNG enhances security for device-to-chip, chip-to-chip, and chip-to-system communications.