Design of high-performance, accurate, and approximate Dadda-tree multipliers for image processing applications

Area of Science:

• Computer Engineering
• Digital Systems Design
• Approximate Computing

Background:

• Approximate computing offers a trade-off between accuracy and performance for enhanced efficiency.
• Efficient multiplier architectures are crucial for resource-constrained FPGA platforms.
• Existing multipliers may not meet the demands for high-performance, low-resource applications.

Purpose of the Study:

• To design and implement efficient approximate multiplier architectures for FPGAs.
• To leverage approximate computing principles for improved performance and resource utilization.
• To evaluate the proposed multipliers for error-resilient applications like medical imaging.

Main Methods:

• FPGA implementation of accurate and approximate multiplier units using the Dadda algorithm.
• Novel partial product reduction technique to minimize resources and critical path delay.
• Performance evaluation using power-delay-area product (PDAP) and peak signal-to-noise ratio (PSNR).

Main Results:

• The best-performing approximate 8x8 multiplier achieved a 28% and 37% improvement in PDAP over Xilinx exact and existing approximate multipliers.
• Significant improvement in PSNR observed during image processing across different modalities.
• Demonstrated superior performance in healthcare-related image processing tasks.

Conclusions:

• The proposed approximate multipliers offer a resource-efficient alternative to traditional designs.
• The novel technique effectively reduces resource utilization and critical path delay on FPGAs.
• The multipliers show strong potential for applications requiring error resilience, particularly in medical imaging.