Common-mode control and confinement inversion of electrostatically defined quantum dots in a commercial CMOS process.

Area of Science:

• Semiconductor Physics
• Quantum Computing

Background:

• Scalable qubit architectures are essential for advancing quantum computing.
• Silicon-on-insulator (SOI) CMOS technology offers a promising platform for fabricating quantum devices.
• Quantum dots (QDs) confined in semiconductor channels are a leading candidate for qubit implementation.

Purpose of the Study:

• To present a calibrated model of a commercial nanostructure for quantum dot formation.
• To experimentally verify the predictions of the developed simulation model.
• To demonstrate the feasibility of controlling and tuning quantum dots in SOI CMOS devices for scalable qubit applications.

Main Methods:

• Utilized the QTCAD® simulation tool for modeling commercial nanostructures.
• Employed a combination of common-mode source-drain voltage and back gate voltage to form quantum dots.
• Varied barrier gate voltages to achieve effective detuning of quantum dot energy levels.
• Performed experimental verification of all model predictions.

Main Results:

• Successfully formed quantum dots in the channel of industry-standard fully depleted SOI CMOS structures.
• Demonstrated precise control over the amount and modification of quantum dots.
• Achieved effective detuning of energy levels within the quantum dots by adjusting barrier gate voltages.
• Validated all model predictions through experimental results.

Conclusions:

• The developed QTCAD® model accurately simulates quantum dot formation in commercial SOI CMOS devices.
• This approach enables controlled fabrication and tuning of quantum dots, essential for scalable qubit architectures.
• Simulating and optimizing quantum dot device designs before fabrication is feasible, accelerating the development of quantum computing hardware.